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a microchip technology company ?2011 silicon storage technology, inc. ds25080a 11/11 not recommended for new designs www.microchip.com features ? single 3.0-3.6v read and write operations ? serial interface architecture ? spi compatible: mode 0 and mode 3 ? 33 mhz max clock frequency ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption: ? active read current: 7 ma (typical) ? standby current: 8 a (typical) ? flexible erase capability ? uniform 4 kbyte sectors ? uniform 32 kbyte overlay blocks ? fast erase and byte-program: ? chip-erase time: 70 ms (typical) ? sector- or block-erase time: 18 ms (typical) ? byte-program time: 14 s (typical) ? auto address increment (aai) programming ? decrease total chip programming time over byte-pro- gram operations ? end-of-write detection ? software status ? hold pin (hold#) ? suspends a serial sequence to the memory without deselecting the device ? write protection (wp#) ? enables/disables the lock-down function of the status register ? software write protection ? write protection through block-protection bits in status register ? temperature range ? commercial: 0c to +70c ? industrial: -40c to +85c ? extended: -20c to +85c ? packages available ? 8-lead soic 150 mil body width for sst25lf020a ? 8-contact wson (5mm x 6mm) ? all non-pb (lead-free) devices are rohs compliant 2 mbit spi serial flash sst25lf020a sst serial flash family features a four-wire, spi-compatible interface that allowsfor a low pin-count package occupying less board space and ultimately lowering total system costs. sst25lf020a spi serial flash memory is manufactured with sst proprietary, high performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufac- turability compared with alternate approaches. not recommended for new designs. please use sst25vf020b downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 2 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company product description sst?s serial flash family features a four-wire, spi-compatible interface that allows for a low pin- count package occupying less board space and ultimately lowering total system costs. sst25lf020a spi serial flash memories are manufactured with sst?s proprietary, high perfor- mance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst25lf020a devices significantly improve performance, while lowering power consumption. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash memory technologies. the sst25lf020a devices operate with a single 3.0-3.6v power supply. the sst25lf020a devices are offered in an 8-lead soic 150 mil body width (sa) pac kage, and in an 8-contact wson package. see figure 2 for the pin assignments. downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 3 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company block diagram figure 1: functional block diagram 1242 b1.0 i/o buffers and data latches superflash memory x - decoder control logic address buffers and latches ce# y - decoder sck si so wp# hold# serial interface downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 4 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company pin description figure 2: pin assignments table 1: pin description symbol pin name functions sck serial clock to provide the timing of the serial interface. commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. si serial data input to transfer commands, addresses, or data serially into the device. inputs are latched on the rising edge of the serial clock. so serial data output to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock. ce# chip enable the device is enabled by a high to low transition on ce#. ce# must remain low for the duration of any command sequence. wp# write protect the write protect (wp#) pin is used to enable/disable bpl bit in the status register. hold# hold to temporarily stop serial communication with spi flash memory without resetting the device. v dd power supply to provide power supply (3.0-3.6v). v ss ground t1.0 25080 8-lead soic 8-contact wson 12 3 4 87 6 5 ce# so wp# v ss top view v dd hold#sck si 1242 08-wson p2.0 12 3 4 87 6 5 ce# so wp# v ss v dd hold#sck si top view 1242 08-soic p1.0 downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 5 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company memory organization the sst25lf020a superflash memory array is organized in 4 kbyte sectors with 32 kbyte overlay blocks. device operation the sst25lf020a is accessed through the spi (serial peripheral interface) bus compatible protocol. the spi bus consist of four control lines; chip enable (ce#) is used to select the device, and data is accessed through the serial data input (si), serial data output (so), and serial clock (sck). the sst25lf020a supports both mode 0 (0,0) and mode 3 (1,1) of spi bus operations. the differ- ence between the two modes, as shown in figure 3, is the state of the sck signal when the bus mas- ter is in stand-by mode and no data is being transferred. the sck signal is low for mode 0 and sck signal is high for mode 3. for both modes, the serial data in (si) is sampled at the rising edge of the sck clock signal and the serial data output (so) is driven after the falling edge of the sck clock sig- nal. figure 3: spi protocol 1242 f02.0 mode 3 sck si so ce# mode 3 don t care bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high impedance msb msb downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 6 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company hold operation hold# pin is used to pause a serial sequence underway with the spi flash memory without resetting the clocking sequence. to activate the hold# mode, ce# must be in active low state. the hold# mode begins when the sck active low state coincides with the falling edge of the hold# signal. the hold mode ends when the hold# signal?s rising edge coincides with the sck active low state. if the falling edge of the hold# signal does not coincide with the sck active low state, then the device enters hold mode when the sck next reaches the active low state. similarly, if the rising edge of the hold# signal does not coincide with the sck active low state, then the device exits in hold mode when the sck next reaches the active low state. see figure 4 for hold condition waveform. once the device enters hold mode, so will be in high-impedance state while si and sck can be v il or v ih . if ce# is driven active high during a hold condition, it resets the internal logic of the device. as long as hold# signal is low, the memory remains in the hold condition. to resume communication with the device, hold# must be driven active high, and ce# must be driven active low. see figure 19 for hold timing. figure 4: hold condition waveform write protection sst25lf020a provides software write protection. the write protect pin (wp#) enables or disables the lock-down function of the status register. the block-protection bits (bp1, bp0, and bpl) in the sta- tus register provide write protection to the memory array and the status register. see table 4 for block- protection description. active hold active hold active 1242 f03.0 sck hold# downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 7 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company write protect pin (wp#) the write protect (wp#) pin enables the lock-down function of the bpl bit (bit 7) in the status register. when wp# is driven low, the execution of the write-status-register (wrsr) instruction is determined by the value of the bpl bit (see table 2). when wp# is high, the lock-down function of the bpl bit is disabled. status register the software status register provides status on whether the flash memory array is available for any read or write operation, whether the device is write enabled, and the state of the memory write pro- tection. during an internal erase or program operation, the status register may be read only to deter- mine the completion of an operation in progress. table 3 describes the function of each bit in the software status register. busy the busy bit determines whether there is an internal erase or program operation in progress. a ?1? for the busy bit indicates the device is busy with an operation in progress. a ?0? indicates the device is ready for the next valid operation. table 2: conditions to execute write-status-register (wrsr) instruction wp# bpl execute wrsr instruction l 1 not allowed l 0 allowed h x allowed t2.0 25080 table 3: software status register bit name function default at power-up read/write 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0r 2 bp0 indicate current level of block write protection (see table 4) 1 r/w 3 bp1 indicate current level of block write protection (see table 4) 1 r/w 4:5 res reserved for future use 0 n/a 6 aai auto address increment programming status 1 = aai programming mode 0 = byte-program mode 0r 7 bpl 1 = bp1, bp0 are read-only bits 0 = bp1, bp0 are read/writable 0 r/w t3.0 25080 downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 8 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company write enable latch (wel) the write-enable-latch bit indicates the status of the internal memory write enable latch. if the write-enable-latch bit is set to ?1?, it indicates the device is write enabled. if the bit is set to ?0? (reset), it indicates the device is not write enabled and does not accept any memory write (program/erase) commands. the write-enable-latch bit is automatically reset under the following conditions: ? power-up ? write-disable (wrdi) instruction completion ? byte-program instruction completion ? auto address increment (aai) programming reached its highest memory address ? sector-erase instruction completion ? block-erase instruction completion ? chip-erase instruction completion block protection (bp1, bp0) the block-protection (bp1, bp0) bits define the size of the memory area, as defined in table 4, to be software protected against any memory write (program or erase) operations. the write-status-regis- ter (wrsr) instruction is used to program the bp1 and bp0 bits as long as wp# is high or the block- protect-lock (bpl) bit is 0. chip-erase can only be executed if block-protection bits are both 0. after power-up, bp1 and bp0 are set to 1. block protection lock-down (bpl) wp# pin driven low (v il ), enables the block-protection-lock-down (bpl) bit. when bpl is set to 1, it prevents any further alteration of the bpl, bp1, and bp0 bits. when the wp# pin is driven high (v ih ), the bpl bit has no effect and its value is ?don?t care?. after power-up, the bpl bit is reset to 0. auto address increment (aai) the auto address increment programming-status bit provides status on whether the device is in aai programming mode or byte-program mode. the default at power up is byte-program mode. table 4: software status register block protection 1 1. default at power-up for bp1 and bp0 is ?11?. protection level status register bit protected memory area bp1 bp0 2 mbit 0 0 0 none 1 (1/4 memory array) 0 1 030000h-03ffffh 2 (1/2 memory array) 1 0 020000h-03ffffh 3 (full memory array) 1 1 000000h-03ffffh t4.0 25080 downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 9 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company instructions instructions are used to read, write (erase and program), and configure the sst25lf020a. the instruction bus cycles are 8 bits each for commands (op code), data, and addresses. prior to execut- ing any byte-program, auto address increment (aai) programming, sector-erase, block-erase, or chip-erase instructions, the write-enable (wren) instruction must be executed first. the complete list of the instructions is provided in table 5. all instructions are synchronized off a high to low transition of ce#. inputs will be accepted on the rising edge of sck starting with the most significant bit. ce# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read-id and read-status-register instructions). any low to high transition on ce#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. instruction commands (op code), addresses, and data are all input from the most significant bit (msb) first. table 5: device operation instructions 1 1. a ms = most significant address a ms =a 17 for sst25lf020a address bits above the most significant bit of each density can be v il or v ih cycle type/ operation 2,3 2. operation: s in = serial in, s out = serial out 3. x = dummy input cycles (v il or v ih ); - = non-applicable cycles (cycles are not necessary) max freq mhz bus cycle 4 4. one bus cycle is eight clock periods. 123456 s in s out s in s out s in s out s in s out s in s out s in s out read 20 03h hi-z a 23 - a 16 hi-z a 15 - a 8 hi-z a 7 -a 0 hi-z x d out high-speed-read 33 0bh hi-z a 23 - a 16 hi-z a 15 - a 8 hi-z a 7 -a 0 hi-z x x x d out sector-erase 5,6 5. sector addresses: use a ms -a 12 , remaining addresses can be v il or v ih 6. prior to any byte-program, aai-program, sector-erase, block-erase, or chip-erase operation, the write-enable (wren) instruction must be executed. 20h hi-z a 23 - a 16 hi-z a 15 - a 8 hi-z a 7 -a 0 hi-z - - block-erase 5,7 52h hi-z a 23 - a 16 hi-z a 15 - a 8 hi-z a 7 -a 0 hi-z - - chip-erase 6 60h hi-z - - ------ byte-program 6 02h hi-z a 23 - a 16 hi-z a 15 - a 8 hi-z a 7 -a 0 hi-z d in hi-z auto address increment (aai) single-byte program 6,8 afh hi-z a 23 - a 16 hi-z a 15 - a 8 hi-z a 7 -a 0 hi-z d in hi-z read-status-register(rdsr) 05h hi-z x d out - note 9 - note 9 - note 9 enable-write-status-register (ewsr) 10 50h hi-z - - ------ write-status-register(wrsr) 10 01h hi-z data hi-z - - -. - - - write-enable (wren) 06h hi-z - - ------ write-disable (wrdi) 04h hi-z - - ------ read-id 90h or abh hi-z 00h hi-z 00h hi-z id addr 11 hi-z x d out 12 t5.0 25080 downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 10 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company read (20 mhz) the read instruction supports up to 20 mhz, it outputs the data starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low to high transition on ce#. the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automati- cally increment to the beginning (wrap-around) of the address space, i.e. for 2 mbit density, once the data from address location 3ffffh had been read, the next output will be from address location 00000h. the read instruction is initiated by executing an 8-bit command, 03h, followed by address bits [a 23 - a 0 ]. ce# must remain active low for the duration of the read cycle. see figure 5 for the read sequence. figure 5: read sequence 7. block addresses for: use a ms -a 15 , remaining addresses can be v il or v ih 8. to continue programming to the next sequential address location, enter the 8-bit command, afh, followed by the data to be programmed. 9. the read-status-register is continuous with ongoing clock cycles until terminated by a low to high transition on ce#. 10. the enable-write-status-register (ewsr) instruction and the write-status-register (wrsr) instruction must work in conjunction of each other. the wrsr instruction must be executed immediately (very next bus cycle) after the ewsr instruction to make both instructions effective. 11. manufacturer?s id is read with a 0 =0, and device id is read with a 0 =1. all other address bits are 00h. the manufacturer and device id output stream is continuous until terminated by a low to high transition on ce# 12. device id = 43h for sst25lf020a 1242 f04.0 ce# so si sck add. 012345678 add. add. 03 high impedance 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 11 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company high-speed-read (33 mhz) the high-speed-read instruction supporting up to 33 mhz is initiated by executing an 8-bit command, 0bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce# must remain active low for the duration of the high-speed-read cycle. see figure 6 for the high-speed-read sequence. following a dummy byte (8 clocks input dummy cycle), the high-speed-read instruction outputs the data starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low to high transition on ce#. the internal address pointer will auto- matically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 2 mbit density, once the data from address location 03ffffh has been read, the next output will be from address location 000000h. figure 6: high-speed-read sequence byte-program the byte-program instruction programs the bits in the selected byte to the desired data. the selected byte must be in the erased state (ffh) when initiating a program operation. a byte-program instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the byte-program instruction. the byte-program instruction is initiated by executing an 8-bit command, 02h, followed by address bits [a 23 -a 0 ]. following the address, the data is input in order from msb (bit 7) to lsb (bit 0). ce# must be driven high before the instruction is exe- cuted. the user may poll the busy bit in the software status register or wait t bp for the completion of the internal self-timed byte-program operation. see figure 7 for the byte-program sequence. figure 7: byte-program sequence 1242 f05.0 ce# so si sck add. 012345678 add. add. 0b high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 x msb msb msb mode 0 mode 3 d out d out d out d out 80 71 72 d out note: x = dummy byte: 8 clocks input dummy cycle (v il or v ih ) 1242 f06.0 ce# so si sck add. 012345678 add. add. d in 02 high impedance 15 16 23 24 31 32 39 mode 0 mode 3 msb msb msb lsb downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 12 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company auto address increment (aai) program the aai program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. this feature decreases total programming time when the entire mem- ory array is to be programmed. an aai program instruction pointing to a protected memory area will be ignored. the selected address range must be in the erased state (ffh) when initiating an aai program instruction. prior to any write operation, the write-enable (wren) instruction must be executed. the aai program instruction is initiated by executing an 8-bit command, afh, followed by address bits [a 23 -a 0 ]. follow- ing the addresses, the data is input sequentially from msb (bit 7) to lsb (bit 0). ce# must be driven high before the aai program instruction is executed. the user must poll the busy bit in the software status register or wait t bp for the completion of each internal self-timed byte-program cycle. once the device completes programming byte, the next sequential address may be program, enter the 8-bit command, afh, followed by the data to be programmed. when the last desired byte had been pro- grammed, execute the write-disable (wrdi) instruction, 04h, to terminate aai. after execution of the wrdi command, the user must poll the status register to ensure the device completes programming. see figure 8 for aai programming sequence. there is no wrap mode during aai programming; once the highest unprotected memory address is reached, the device will exit aai operation and reset the write-enable-latch bit (wel = 0). figure 8: auto address increment (aai) program sequence ce# si sck a[23:16] a[15:8] a[7:0] af data byte 1 af databyte2 ce# si so sck write disable (wrdi) instruction to terminate aai operation read status register (rdsr) instruction to verify end of aai operation 04 last data byte af 05 d out mode 3 mode 0 t bp t bp t bp 1242 f07.0 012345678 3233343536373839 1516 2324 31 0123456789101112131415 01 01234567 0123456789101112131415 0123456789101112131415 downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 13 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company sector-erase the sector-erase instruction clears all bits in the selected 4 kbyte sector to ffh. a sector-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write- enable (wren) instruction must be executed. ce# must remain active low for the duration of the any command sequence. the sector-erase instruction is initiated by executing an 8-bit command, 20h, fol- lowed by address bits [a 23 -a 0 ]. address bits [a ms -a 12 ](a ms = most significant address) are used to determine the sector address (sa x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t se for the completion of the internal self-timed sector-erase cycle. see figure 9 for the sector-erase sequence. figure 9: sector-erase sequence block-erase the block-erase instruction clears all bits in the selected 32 kbyte block to ffh. a block-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write- enable (wren) instruction must be executed. ce# must remain active low for the duration of any com- mand sequence. the block-erase instruction is initiated by executing an 8-bit command, 52h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 15 ](a ms = most significant address) are used to deter- mine block address (ba x ), remaining address bits can be v il or v ih . ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t be for the com- pletion of the internal self-timed block-erase cycle. see figure 10 for the block-erase sequence. figure 10: block-erase sequence ce# so si sck add. 012345678 add. add. 20 high impedance 15 16 23 24 31 mode 0 mode 3 1242 f08.0 msb msb ce# so si sck add. 012345678 add. add. 52 high impedance 15 16 23 24 31 mode 0 mode 3 1242 f09.0 msb msb downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 14 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company chip-erase the chip-erase instruction clears all bits in the device to ffh. a chip-erase instruction will be ignored if any of the memory area is protected. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the chip-erase instruction sequence. the chip-erase instruction is initiated by executing an 8-bit command, 60h. ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t ce for the completion of the internal self-timed chip-erase cycle. see figure 11 for the chip-erase sequence. figure 11: chip-erase sequence read-status-register (rdsr) the read-status-register (rdsr) instruction allows reading of the status register. the status register may be read at any time even during a write (program/erase) operation. when a write operation is in progress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce# must be driven low before the rdsr instruction is entered and remain low until the status data is read. read-status-register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the ce#. see figure 12 for the rdsr instruction sequence. figure 12: read-status-register (rdsr) sequence ce# so si sck 01234567 60 high impedance mode 0 mode 3 1242 f10.0 msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1242 f11.0 mode 3 sck si so ce# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 mode 0 high impedance status register out msb msb downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 15 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company write-enable (wren) the write-enable (wren) instruction sets the write-enable-latch bit to 1 allowing write operations to occur. the wren instruction must be executed prior to any write (program/erase) operation. ce# must be driven high before the wren instruction is executed. figure 13: write enable (wren) sequence write-disable (wrdi) the write-disable (wrdi) instruction resets the write-enable-latch bit and aai bit to 0 disabling any new write operations from occurring. ce# must be driven high before the wrdi instruction is exe- cuted. figure 14: write disable (wrdi) sequence enable-write-status-register (ewsr) the enable-write-status-register (ewsr) instruction arms the write-status-register (wrsr) instruction and opens the status register for alteration. the enable-write-status-register instruction does not have any effect and will be wasted, if it is not followed immediately by the write-status-regis- ter (wrsr) instruction. ce# must be driven low before the ewsr instruction is entered and must be driven high before the ewsr instruction is executed. ce# so si sck 01234567 06 high impedance mode 0 mode 3 1242 f12.0 msb ce# so si sck 01234567 04 high impedance mode 0 mode 3 1242 f13.0 msb downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 16 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company write-status-register (wrsr) the write-status-register instruction works in conjunction with the enable-write-status-register (ewsr) instruction to write new values to the bp1, bp0, and bpl bits of the status register. the write- status-register instruction must be executed immediately after the execution of the enable-write-sta- tus-register instruction (very next instruction bus cycle). this two-step instruction sequence of the ewsr instruction followed by the wrsr instruction works like sdp (software data protection) com- mand structure which prevents any accidental alteration of the status register values. the write-sta- tus-register instruction will be ignored when wp# is low and bpl bit is set to ?1?. when the wp# is low, the bpl bit can only be set from ?0? to ?1? to lock-down the status register, but cannot be reset from ?1? to ?0?. when wp# is high, the lock-down function of the bpl bit is disabled and the bpl, bp0, and bp1 bits in the status register can all be changed. as long as bpl bit is set to 0 or wp# pin is driven high (v ih ) prior to the low-to-high transition of the ce# pin at the end of the wrsr instruction, the bp0, bp1, and bpl bit in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as altering the bp0 and bp1 bit at the same time. see table 2 for a summary description of wp# and bpl functions. ce# must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wrsr instruction is executed. see figure 15 for ewsr and wrsr instruc- tion sequences. figure 15: enable-write-status-register (ewsr) and write-status-register (wrsr) sequence 1242 f14.0 mode 3 high impedance mode 0 status register in 76543210 msb msb msb 01 mode 3 sck si so ce# mode 0 50 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 17 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company read-id the read-id instruction identifies the devices as sst25lf020a and manufacturer as sst. the device information can be read from executing an 8-bit command, 90h or abh, followed by address bits [a 23 - a 0 ]. following the read-id instruction, the manufacturer?s id is located in address 00000h and the device id is located in address 00001h. once the device is in read-id mode, the manufacturer?s and device id output data toggles between address 00000h and 00001h until terminated by a low to high transition on ce#. figure 16: read-id sequence table 6: product identification address data manufacturer?s id 00000h bfh device id sst25lf020a 00001h 43h t6.0 25080 1242 f15.0 ce# so si sck 00 012345678 00 add 1 90 or ab high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 bf device id bf device id note: the manufacturer s and device id output stream is continuous until terminated by a low to high transition on ce#. 1. 00h will output the manfacturer s id first and 01h will output device id first before toggling between the two. high impedance mode 3 mode 0 msb msb msb downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 18 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company electrical specifications absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maxi- mum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reli- ability.) temperature under bias .............................................. -55c to +125c storage temperature ................................................. -65c to +150c d. c. voltage on any pin to ground potential ............................. -0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential .................. -2.0v to v dd +2.0v package power dissipation capability (ta = 25c) ................................... 1.0w surface mount solder reflow temperature ........................... 260c for 10 seconds output short circuit current 1 ................................................... 50ma 1. output shorted for no more than one second. no more than one output shorted at a time. table 7: operating range range ambient temp v dd commercial 0c to +70c 3.0-3.6v industrial -40c to +85c 3.0-3.6v extended -20c to +85c 3.0-3.6v t7.1 25080 table 8: ac conditions of test 1 1. see figures 21 and 22 input rise/fall time output load 5ns c l =30pf t8.1 25080 table 9: dc operating characteristics v dd = 3.0-3.6v symbol parameter limits test conditions min max units i ddr read current 10 ma ce#=0.1 v dd /0.9 v dd @20 mhz, so=open i ddw program and erase current 30 ma ce#=v dd i sb standby current 15 a ce#=v dd ,v in =v dd or v ss i li input leakage current 1 a v in =gnd to v dd ,v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd ,v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 0.7 v dd vv dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t9.0 25080 downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 19 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company table 10: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. v dd min to read operation 10 s t pu-write 1 v dd min to write operation 10 s t10.0 25080 table 11: capacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. output pin capacitance v out =0v 12pf c in 1 input capacitance v in =0v 6pf t11.0 25080 table 12: reliability characteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lth 1 latch up 100 + i dd ma jedec standard 78 t12.0 25080 downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 20 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company table 13: ac operating characteristics v dd = 3.0-3.6v limits 20 mhz 33 mhz symbol parameter min max min max units f clk serial clock frequency 20 33 mhz t sckh serial clock high time 20 13 ns t sckl serial clock low time 20 13 ns t ces 1 ce# active setup time 20 12 ns t ceh 1 ce# active hold time 20 12 ns t chs 1 ce# not active setup time 10 10 ns t chh 1 ce# not active hold time 10 10 ns t cph ce# high time 100 100 ns t chz ce# high to high-z output 20 14 ns t clz sck low to low-z output 0 0 ns t ds data in setup time 5 3 ns t dh data in hold time 5 3 ns t hls hold# low setup time 10 10 ns t hhs hold# high setup time 10 10 ns t hlh hold# low hold time 15 10 ns t hhh hold# high hold time 10 10 ns t hz hold# low to high-z output 20 14 ns t lz hold# high to low-z output 20 14 ns t oh output hold from sck change 0 0 ns t v output valid from sck 20 12 ns t se sector-erase 25 25 ms t be block-erase 25 25 ms t sce chip-erase 100 100 ms t bp byte-program 20 20 s t13.0 25080 1. relative to sck. downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 21 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company figure 17: serial input timing diagram figure 18: serial output timing diagram high-z high-z ce# so si sck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 1242 f16.0 1242 f17.0 ce# si so sck msb t clz t v t sckh t chz t oh t sckl lsb downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 22 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company figure 19: hold timing diagram figure 20: power-up timing diagram t hz t lz t hhh t hls t hlh t hhs 1242 f18.0 hold# ce# sck so si time v dd min v dd max v dd device fully accessible t pu-read t pu-write chip selection is not allowed. all commands are rejected by the device. 1242 f19.0 downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 23 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company figure 21: ac input/output reference waveforms figure 22: a test load example 1242 f20.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic ?1? and v ilt (0.1v dd ) for a logic ?0?. mea- surement reference points for inputs and outputs are v ht (0.7v dd ) and v lt (0.3v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v ht -v high test v lt -v low test v iht -v input high test v ilt -v input low test 1242 f21.0 to tester to dut c l downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 24 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company product ordering information valid combinations for sst25lf020a sst25lf020a-33-4c-sae SST25LF020A-33-4C-QAE sst25lf020a-33-4i-sae sst25lf020a-33-4i-qae sst25lf020a-33-4e-sae sst25lf020a-33-4e-qae note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combi- nations. sst 25 lf 020a - 33 - 4i - qae xx xx xxxx - xx - xx - xxx environmental attribute e 1 = non-pb package modifier a = 8 leads or contacts package type s = soic 150 mil body width q = wson operation temperature c = commercial = 0c to +70c i = industrial = -40c to +85c e = extended = -20c to +85c minimum endurance 4 = 10,000 cycles operating frequency 33 = 33 mhz device density 020 = 2 mbit voltage l = 3.0-3.6v product series 25 = serial peripheral interface flash memory 1. environmental suffix ?e? denotes non-pb sol- der. sst non-pb solder devices are ?rohs com- pliant?. downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 25 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company packaging diagrams figure 23: 8-lead small outline integrated circuit (soic) 150 mil body width (4.9mm x 6mm) sst package code: sa 08-soic-5x6-sa-8 note: 1. complies with jedec publication 95 ms-012 aa dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. top view side view end view 5.04.8 6.205.80 4.003.80 pin #1 identifier 0.510.33 1.27 bsc 0.250.10 1.751.35 7 4 places 0.250.19 1.270.40 45 7 4 places 08 1mm downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 26 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company figure 24: 8-contact very-very-thin small outline no-lead (wson) sst package code: qa note: 1. all linear dimensions are in millimeters (max/min). 2. untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. the external paddle is electrically connected to the die back-side and possibly to certain v ss leads. this paddle can be soldered to the pc board; it is suggested to connect this paddle to the v ss of the unit. connection of this paddle to any other voltage potential can result in shorts and/or electrical malfunction of the device. 8-wson-5x6-qa-9.0 4.0 1.27 bsc pin #1 0.480.35 0.076 3.4 5.00 0.10 6.00 0.10 0.05 max 0.700.50 0.800.70 0.800.70 pin #1 corner top view bottom view cross section side view 1mm 0.2 downloaded from: http:///
?2011 silicon storage technology, inc. ds25080a 11/11 27 2 mbit spi serial flash sst25lf020a not recommended for new designs a microchip technology company table 14: revision history revision description date 00 ? initial release of s71242 aug 2003 01 ? added new 8-soic (s2a) package and associated mpns oct 2003 02 ? 2004 data book ? updated the package outline for s2a dec 2003 03 ? document status changed from ?advance information? to ?preliminary specifications? ? added commercial and extended temperatures and associated mpns jun 2004 04 ? revised absolute max. stress ratings for surface mount solder reflow temp. ? migrated document from preliminary specifications to data sheet nov 2005 05 ? updated qa package drawing to version 9. ? removed leaded part numbers. ? added footnote to product ordering information section. jan 2006 06 ? end of life all valid combinations of sst25lf040a. see s71242(01) mar 2009 07 ? removed 4mbit information inadvertently missed in last eol revision jan 2010 a ? applied new document format ? released document under letter revision system ? updated spec number from s71242 to ds25080 nov 2011 ? 2011 silicon storage technology, inc?a microchip technology company. all rights reserved. sst, silicon storage technology, the sst logo, superflash, mtp, and flashflex are registered trademarks of silicon storage tech- nology, inc. mpf, sqi, serial quad i/o, and z-scale are trademarks of silicon storage technology, inc. all other trademarks and registered trademarks mentioned herein are the property of their respective owners. specifications are subject to change without notice. refer to www.microchip.com for the most recent documentation. for the most current package drawings, please see the packaging specification located at http://www.microchip.com/packaging. memory sizes denote raw storage capacity; actual usable capacity may be less. sst makes no warranty for the use of its products other than those expressly contained in the standard terms and conditions of sale. for sales office locations and information, please see www.microchip.com. silicon storage technology, inc. a microchip technology company www.microchip.com isbn:978-1-61341-683-9 downloaded from: http:///

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